During fabrication of gate electrodes, wet approaches to remove/pattern high-k gate dielectrics almost invariably induces unwanted side effect and dry approaches cause loss of the gate spacers which induces subsequent silicide shorting problems.
U.S. Pat. No. 6,271,094 B1 to Boyd et al. describes a high-k gate oxide and gate process.
U.S. Pat. No. 6,063,698 to Tseng et al. describes another high-k gate oxide and gate process.
U.S. Pat. No. 5,783,479 to Lin et al. describes a structure and method for manufacturing FETs having T-shaped gates.
U.S. Pat. No. 6,255,221 B1 to Hudson et al. describes methods and systems for etching dielectric layers in a high density plasma etcher.
Accordingly, it is an object of one or more embodiments of the present invention to provide an improved method of patterning gate electrodes having an underlying high-k gate dielectric layer.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate is provided. A high-k dielectric layer is formed over the substrate. A gate electrode layer is formed over the high-k dielectric layer. The gate electrode layer is patterned to form a patterned gate electrode layer, the patterned gate electrode -layer having exposed side walls and a top. Sidewall spacers are formed over the exposed side walls of the patterned gate electrode layer, the sidewall spacers having tops. The patterned gate electrode layer is etched to pull the top of the patterned gate electrode layer down from the tops of the sidewall spacers. The exposed portions of the high-k dielectric layer not under the sidewall spacers and the pulled-down patterned gate electrode layer are removed.